One-time programmable (OTP) memories are an increasingly important component of modern electronics. Typically, OTP memories require a bias current to perform the read operation. In older, well controlled processes, the allowable ratio of the on-current of the OTP memory cell to the bias current can be 10/1 or greater. In newer (leaky) processes, the allowable bias current ratio can be as low as 3/1 and is shrinking. Tightening ranges require a precision current reference to maintain a reliable read function.
FIG. 1A is a schematic circuit diagram illustrating a prior art OTP bit measurement circuit 100. Circuit 100 includes an OTP bit memory element 110 comprising a programmable current source. The programmable current source 110 is coupled to a resistor 120, the other end of which is coupled to ground. The OTP bit memory element 110 is also coupled at a node Vmeasurement 125 to an input of a comparator 130, which compares Vmeasurement to a threshold voltage. An output of the comparator 130 is coupled to a Voutput node 135. For more information about OTP sensors themselves, please see, for example, “COP8&L88GW microCMOS One-Time Programmable (OTP) Microcontroller,” Literature Number SNOS782A, Copyright 2011, Texas Instruments Incorporated, which is hereby incorporated by reference in its entirety.
In operation, the OTP bit memory element 110 is programmed either as an “on” (programmed) state, representing a digital value of 1, or an “off” (unprogrammed) state, representing a digital value of 0. If the OTP bit memory element 110 is programmed as an “off,” or “not programmed,” state, substantially no, or very little current flows from the OTP bit memory element 110 through the resistor 120, and therefore Vmeasurement node 125 is pulled to ground by resistor 120 and therefore the comparator 130 outputs a logical 0. If, on the other hand, the OTP bit memory element 110 is programmed as “on,” or “programmed,” the bit memory element produces a set amount of current that flows through the resistor 120, and therefore Vmeasurement node 125 approaches a voltage proportional to the current of the OTP bit memory 110, and therefore the comparator 130 outputs a logical “1.” The power supply voltage VDD is generally product and process dependent, but can be, for example, 3.6V.
FIG. 1B illustrates an array 150 of OTP bit memory elements 110-113 that are selectively coupleable to be read by the comparator 130. In the array 150, an OTP bit memory element 110-113 can be selectively coupled to the resistor 120 and the comparator 130 through its corresponding switch 115-118.
FIG. 1C illustrates an array 170 comprising a plurality of rows 175, 177 of OTP bit memory elements. The array 170 is a densely packed arrangement of minimum sized PMOS floating gate devices (i.e. OTP cells). Each row 175, 177 represents a data word and includes a number, for example, 8, of bit memory elements. The array includes a read line 171 and a write line 173 for each bit position. Thus, in an architecture that uses 8-bit words, the array 170 includes 8 read lines and 8 write lines. Each row 175, 177 has an associated wordline (not shown). Each wordline is coupled to all of the gates in its associated row. Thus activating/deactivating the wordline turns on/off all of the transistors in that row. When a given wordline is activated, each read/write line 171, 173 only operates on the corresponding bit of the selected row each read/write line 171, 173 is a shared bus amongst all the words. The read/write lines 171, 173 are used by an array of sense amplifiers connected to each read/write line to write data to and read data from the bit memory cells.
There are problems with the circuits 100, 150, and 170 of FIGS. 1A-1C that rely upon the resistor 120. For example, due to a constant current bleed through the resistor 120, the resistor 120 value does not track the variation of the OTP bit memory element for either programmed or unprogrammed states. Also, the size of the resistor 120 must be precise. Typically, the value of the resistor 120 is set by the supply voltage and the maximum Ioff current of the bit memory element, such as might be seen from an unprogrammed OTP. For example, in some example implementations, the resistance of resistor 120 is set as R=VDD/(2*Ioff_max). Finally, the lifetime data retention has no tracking between the ‘read resistor’ and the OTP current values. Therefore, there is a need in the art to address at least some of the issues associated with conventional OTP bit measurement circuits.